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1 pf912-04 micro mini s1c60n05 4-bit single chip microcomputer s1c6200b core cpu low voltage and low power built-in lcd driver built-in a/d converter (2ch.) introduction each member of the s1c60n05 series of single chip microcomputers feature a 4-bit s1c6200b core cpu, 1,536 words of rom (12 bits per word), 80 words of ram (4 bits per word), an lcd driver, 4 bits for input ports (k00?03), 4 bits for output ports (r00?03), one 4-bit i/o port (p00?03), clock timer and a/d converter. because of their low voltage operation and low power consumption, the s1c60n05 series are ideal for a wide range of applications. configuration the s1c60n05 series are configured as follows, depending on the supply voltage. model supply voltage oscillation circuits 1.8 3.5 v 1.2 2.0 v s1c60n05 S1C60L05 crystal or cr crystal or cr features core cpu ................................................... s1c6200b built-in oscillation circuit............................. crystal or cr oscillation circuit, 32,768 hz (typ.) nstruction set .............................................. 100 instructions rom capacity ............................................ 1,536 words 12 bits ram capacity (data ram) ......................... 80 words 4 bits input port .................................................... 4 bits (supplementary pull-down resistors may be used) output port ................................................. 4 bits (piezo buzzer and programmable frequency output can be driven directry by mask option) input/output port ......................................... 4 bits lcd driver .................................................. 20 segments 4 common duty (or 3 and 2 common duty) timer .......................................................... clock timer a/d converter ............................................. cr oscillation type a/d converter built-in (2 channels) interrupts: external interrupt ................................ input port interrupt 1 system internal interrupt ................................. timer interrupt 1 system a/d converter interrupt 1 system supply voltage ........................................... 1.5 v (1.2 2.0 v) S1C60L05 (during a/d conversion) 3.0 v (1.8 3.5 v) s1c60n05 current consumption (typ.) ........................ 0.8 a (crystal oscillation clk = 32,768 hz, when halted) 1.5 a (crystal oscillation clk = 32,768 hz, when executing) supply form ................................................ qfp6-60pin (plastic) or chip low voltage operation products
2 s1c60n05 block diagram pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 n.c. n.c. k00 k01 k02 k03 r00 r01 r02 r03 rs th1 th2 cs n.c. pin no. pin name 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 n.c. adout seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 n.c. pin no. pin name 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 test reset seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 com0 com1 com2 com3 n.c. pin no. pin name 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 n.c. : no connection v l3 v l2 v l1 ca cb v ss v dd osc1 osc2 v s1 p00 p01 p02 p03 n.c. pin no. pin name 31 45 16 30 index 15 1 60 46 s1c60n05 qfp6-60pin com0 3 seg0 19 k00 03 p00 03 r00 03 osc1 osc2 reset test power controller ram 80 words x 4 bits osc system reset control v dd v l1 3 ca cb v s1 v ss adout rs th1 th2 cs interrupt generator input port test port lcd driver i/o port output port timer core cpu s1c6200b a/d converter rom 1,536 words x 12 bits
3 s1c60n05 pin description pin name v dd v ss v s1 v l1 v l2 v l3 ca, cb osc1 osc2 k00 k03 p00 p03 r00 r03 seg0 19 com0 3 cs rs th1, th2 adout reset test function power source (+) terminal power source (-) terminal oscillation and internal logic system regulated voltage output terminal lcd system regulated voltage output terminal lcd system booster output terminal lcd system booster output terminal booster capacitor connecting terminal crystal or cr oscillation input terminal crystal or cr oscillation output terminal input terminal i/o terminal output terminal lcd segment output terminal (convertible to dc output terminal by mask option) lcd common output terminal a/d converter cr oscillation input terminal a/d converter cr oscillation output terminal a/d converter cr oscillation output terminal a/d converter oscillation frequency output terminal initial setting input terminal test input terminal pin no. 52 51 55 48 47 46 49, 50 53 54 3 6 56 59 7 10 18 29 33 40 41 44 14 11 12, 13 17 32 31 in/out (i) (i) o o o o i o i i/o o o o i o o o i i option list 1. device type and lcd voltage 1. e0c6005 (normal type ) lcd 3 v 2. e0c6005 (normal type ) lcd 4.5 v 3. e0c60l05 (low power type <S1C60L05>) lcd 3 v 4. e0c60l05 (low power type <S1C60L05>) lcd 4.5 v 2. multiple key entry reset combination ........................... 1. not use 2. use k00, k01 3. use k00, k01, k02 4. use k00, k01, k02, k03 3. interrupt noise rejector k00 k03 ..................................... 1. use 2. not use 4. input port pull down resistor k00 .............................................. 1. with resistor 2. gate direct k01 .............................................. 1. with resistor 2. gate direct k02 .............................................. 1. with resistor 2. gate direct k03 .............................................. 1. with resistor 2. gate direct 5. r00 specification output type ........................... 1. dc output 2. buzzer inverted output (control bit is r00) 3. buzzer inverted output (control bit is r01) 4. fout output fout output spacification f2 ............. 1. 1.512[hz] 2. 1,024[hz] 3. 2,048[hz] 4. 4,096[hz] 5. 8,192[hz] f1 ............. 1. 256[hz] 2. 512[hz] 3. 1,024[hz] 4. 2,048[hz] 5. 4,096[hz]
4 s1c60n05 electrical characteristics absolute maximum ratings rating power voltage input voltage (1) input voltage (2) operating temperature storage temperature soldering temperature / time allowable dissipation * 1 ? 1: in case of plastic package (qfp6-60pin). symbol v ss v i v iosc topr tstg tsol p d value -5.0 to 0.5 v ss - 0.3 to 0.5 v ss - 0.3 to 0.5 -20 to 70 -65 to 150 260 c, 10sec (lead section) 250 unit v v v c c mw (v dd =0v) recommended operating conditions s1c60n05 condition power voltage oscillation frequency booster capacitor capacitor between v dd and v s1 symbol v ss f osc1 f osc2 c 1 c 2 remark v dd =0v crystal oscillation cr oscillation, r=420k ? unit v khz khz f f (ta=-20 to 70 c) max. -1.8 80 typ. -3.0 32.768 65 min. -3.5 0.1 0.1 f3 ........... 1. 1,024[hz] 2. 2,048[hz] 3. 4,096[hz] 4. 8,192[hz] 5. 16,384[hz] f4 ............ 1. 2,048[hz] 2. 4,096[hz] 3. 8,192[hz] 4. 16,384[hz] 5. 32,768[hz] output specification ......... 1. complementary 2. pch-opendrain 6. r01 specification output type ........................... 1. dc output 2. buzzer output output specification ......... 1. complementary 2. pch-opendrain 7. output specification (r02, r03) r02 .............................................. 1. complementary 2. pch-opendrain r03 .............................................. 1. complementary 2. pch-opendrain 8. i/o port specification p00 .............................................. 1. complementary 2. pch-opendrain p01 .............................................. 1. complementary 2. pch-opendrain p02 .............................................. 1. complementary 2. pch-opendrain p03 .............................................. 1. complementary 2. pch-opendrain 9. lcd common duty and bias 1. 1/4 duty 1/3 bias 2. 1/3 duty 1/3 bias 3. 1/2 duty 1/3 bias 4. 1/4 duty 1/2 bias 5. 1/3 duty 1/2 bias 6. 1/2 duty 1/2 bias 10.osc1 system clock 1. crystal 2. cr
5 s1c60n05 S1C60L05 condition power voltage oscillation frequency booster capacitor capacitor between v dd and v s1 ? 1: when there is no software control during cr oscillation or crystal oscillation. symbol v ss f osc1 f osc2 c 1 c 2 remark v dd =0v * 1 crystal oscillation cr oscillation, r=420k ? unit v khz khz f f (ta=-20 to 70 c) max. -1.2 80 typ. -1.5 32.768 65 min. -2.0 0.1 0.1 dc characteristics s1c60n05 unit v v v v a a a a ma ma ma ma ma ma a a a a a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc =32.768khz, ta=25 c, v s1 /v l1 v l3 are internal voltage , c 1 =c 2 =0.1 f) max. 0 0 0.8 v ss 0.85 v ss 0.5 40 100 0 -1.0 -1.0 -1.0 -3 -3 -300 typ. min. 0.2 v ss 0.15 v ss v ss v ss 0 10 30 -0.5 3.0 3.0 3.0 3 3 300 characteristic high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current (1) high level input current (2) high level input current (3) low level input current high level output current (1) high level output current (2) high level output current (3) low level output current (1) low level output current (2) low level output current (3) common output current segment output current (during lcd output) segment output current (during dc output) symbol v ih1 v ih2 v il1 v il2 i ih1 i ih2 i ih3 i il i oh1 i oh2 i oh3 i ol1 i ol2 i ol3 i oh4 i ol4 i oh5 i ol5 i oh6 i ol6 v ih1 =0v, no pull down resistor v ih2 =0v, with pull down resistor v ih3 =0v, with pull down resistor v il =v ss v oh1 =0.1 v ss v oh2 =0.1 v ss (built-in protection resistance) v oh3 =-1.0v v ol1 =0.9 v ss v ol2 =0.9 v ss (built-in protection resistance) v ol3 =-2.0v v oh4 =-0.05v v ol4 =v l3 +0.05v v oh5 =-0.05v v ol5 =v l3 +0.05v v oh6 =0.1 v ss v ol6 =0.9 v ss condition k00 k03, p00 p03 reset, test k00 k03, p00 p03 reset, test k00 k03, p00 p03 k00 k03 p00 p03 reset, test k00 k03, p00 p03 reset, test r02, r03, p00 p03 r00, r01 adout r02, r03, p00 p03 r00, r01 adout com0 com3 seg0 seg19 seg0 seg19 S1C60L05 unit v v v v a a a a a a a a a a a a a a a a (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc =32.768khz, ta=25 c, v s1 /v l1 v l3 are internal voltage , c 1 =c 2 =0.1 f) max. 0 0 0.8 v ss 0.85 v ss 0.5 20 100 0 -200 -200 -200 -3 -3 -100 typ. min. 0.2 v ss 0.15 v ss v ss v ss 0 5.0 9.0 -0.5 700 700 700 3 3 130 characteristic high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current (1) high level input current (2) high level input current (3) low level input current high level output current (1) high level output current (2) high level output current (3) low level output current (1) low level output current (2) low level output current (3) common output current segment output current (during lcd output) segment output current (during dc output) symbol v ih1 v ih2 v il1 v il2 i ih1 i ih2 i ih3 i il i oh1 i oh2 i oh3 i ol1 i ol2 i ol3 i oh4 i ol4 i oh5 i ol5 i oh6 i ol6 v ih1 =0v, no pull down resistor v ih2 =0v, with pull down resistor v ih3 =0v, with pull down resistor v il =v ss v oh1 =0.1 v ss v oh2 =0.1 v ss (built-in protection resistance) v oh3 =-0.5v v ol1 =0.9 v ss v ol2 =0.9 v ss (built-in protection resistance) v ol3 =-1.0v v oh4 =-0.05v v ol4 =v l3 +0.05v v oh5 =-0.05v v ol5 =v l3 +0.05v v oh6 =0.1 v ss v ol6 =0.9 v ss condition k00 k03, p00 p03 reset, test k00 k03, p00 p03 reset, test k00 k03, p00 p03 k00 k03 p00 p03 reset, test k00 k03, p00 p03 reset, test r02, r03, p00 p03 r00, r01 adout r02, r03, p00 p03 r00, r01 adout com0 com3 seg0 seg19 seg0 seg19
6 s1c60n05 analog circuit characteristics and current consumption s1c60n05 (normal operating mode) unit v v v a a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 v l3 are internal voltage, c 1 =c 2 =0.1 f ) max. 1/2 v l2 0.9 3/2 v l2 0.9 1.4 5.0 40 typ. v ss 0.8 1.5 30 min. 1/2 v l2 -0.1 3/2 v l2 -0.1 characteristic internal voltage power current consumption symbol v l1 v l2 v l3 i op condition connect 1m ? load resistor between v dd and v l1 (without panel load) connect 1m ? load resistor between v dd and v l2 (without panel load) connect 1m ? load resistor between v dd and v l3 (without panel load) during halt during execution during a/d conversion (halt) without panel load s1c60n05 (heavy load protection mode) unit v v v a a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 v l3 are internal voltage, c 1 =c 2 =0.1 f ) max. 1/2 v l2 0.85 3/2 v l2 0.85 5.5 10.0 41.5 typ. v ss 2.0 5.5 31 min. 1/2 v l2 -0.1 3/2 v l2 -0.1 characteristic internal voltage power current consumption symbol v l1 v l2 v l3 i op condition connect 1m ? load resistor between v dd and v l1 (without panel load) connect 1m ? load resistor between v dd and v l2 (without panel load) connect 1m ? load resistor between v dd and v l3 (without panel load) during halt during execution during a/d conversion (halt) without panel load S1C60L05 (normal operating mode) unit v v v a a a (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 v l3 are internal voltage, c 1 =c 2 =0.1 f ) max. 2 v l1 0.9 3 v l1 0.9 1.4 5.0 40 typ. v ss 0.8 1.5 30 min. 2 v l1 -0.1 3 v l1 -0.1 characteristic internal voltage power current consumption symbol v l1 v l2 v l3 i op condition connect 1m ? load resistor between v dd and v l1 (without panel load) connect 1m ? load resistor between v dd and v l2 (without panel load) connect 1m ? load resistor between v dd and v l3 (without panel load) during halt during execution during a/d conversion (halt) without panel load S1C60L05 (heavy load protection mode) unit v v v a a a (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 v l3 are internal voltage, c 1 =c 2 =0.1 f ) max. 2 v l1 0.85 3 v l1 0.85 5.5 10.0 41.5 typ. v ss 2.0 5.5 31 min. 2 v l1 -0.1 3 v l1 -0.1 characteristic internal voltage power current consumption symbol v l1 v l2 v l3 i op condition connect 1m ? load resistor between v dd and v l1 (without panel load) connect 1m ? load resistor between v dd and v l2 (without panel load) connect 1m ? load resistor between v dd and v l3 (without panel load) during halt during execution during a/d conversion (halt) without panel load
7 s1c60n05 s1c60n05 (cr, normal operating mode) unit v v v a a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc =65khz, ta=25 c, c g =25pf, v s1 /v l1 v l3 are internal voltage, c 1 =c 2 =0.1 f recommended external resistance for cr oscillation=420k ? ) max. 1/2 v l2 0.9 3/2 v l2 0.9 15.0 20.0 52.5 typ. v ss 8.0 15.0 37 min. 1/2 v l2 -0.1 3/2 v l2 -0.1 characteristic internal voltage power current consumption symbol v l1 v l2 v l3 i op condition connect 1m ? load resistor between v dd and v l1 (without panel load) connect 1m ? load resistor between v dd and v l2 (without panel load) connect 1m ? load resistor between v dd and v l3 (without panel load) during halt during execution during a/d conversion (halt) without panel load s1c60n05 (cr, heavy load protection mode) unit v v v a a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc =65khz, ta=25 c, c g =25pf, v s1 /v l1 v l3 are internal voltage, c 1 =c 2 =0.1 f recommended external resistance for cr oscillation=420k ? ) max. 1/2 v l2 0.85 3/2 v l2 0.85 30.0 40.0 57.5 typ. v ss 16.0 30.0 45 min. 1/2 v l2 -0.1 3/2 v l2 -0.1 characteristic internal voltage power current consumption symbol v l1 v l2 v l3 i op condition connect 1m ? load resistor between v dd and v l1 (without panel load) connect 1m ? load resistor between v dd and v l2 (without panel load) connect 1m ? load resistor between v dd and v l3 (without panel load) during halt during execution during a/d conversion (halt) without panel load S1C60L05 (cr, normal operating mode) unit v v v a a a (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc =65khz, ta=25 c, c g =25pf, v s1 /v l1 v l3 are internal voltage, c 1 =c 2 =0.1 f recommended external resistance for cr oscillation=420k ? ) max. 2 v l1 0.9 3 v l1 0.9 15.0 20.0 52.5 typ. v ss 8.0 15.0 37 min. 2 v l1 -0.1 3 v l1 -0.1 characteristic internal voltage power current consumption symbol v l1 v l2 v l3 i op condition connect 1m ? load resistor between v dd and v l1 (without panel load) connect 1m ? load resistor between v dd and v l2 (without panel load) connect 1m ? load resistor between v dd and v l3 (without panel load) during halt during execution during a/d conversion (halt) without panel load S1C60L05 (cr, heavy load protection mode) unit v v v a a a (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc =65khz, ta=25 c, c g =25pf, v s1 /v l1 v l3 are internal voltage, c 1 =c 2 =0.1 f recommended external resistance for cr oscillation=420k ? ) max. 2 v l1 0.85 3 v l1 0.85 30.0 40.0 57.5 typ. v ss 16.0 30.0 45 min. 2 v l1 -0.1 3 v l1 -0.1 characteristic internal voltage power current consumption symbol v l1 v l2 v l3 i op condition connect 1m ? load resistor between v dd and v l1 (without panel load) connect 1m ? load resistor between v dd and v l2 (without panel load) connect 1m ? load resistor between v dd and v l3 (without panel load) during halt during execution during a/d conversion (halt) without panel load
8 s1c60n05 oscillation characteristics oscillation characteristics will vary according to different conditions (elements used, boad pattern). use the following char- acteristics are as reference values. s1c60n05 unit v v pf ppm ppm ppm v m ? (unless otherwise specified: v dd =0v, v ss =-3.0v, crystal: q13mc146, c g =25pf, c d =built-in, ta=25 c) max. 5 10 -3.6 typ. 20 min. -1.8 -1.8 -10 40 200 characteristic oscillation start voltage oscillation stop voltage built-in capacitance (drain) frequency/voltage deviation frequency/ic deviation frequency adjustment range harmonic oscillation start voltage allowable leak resistance symbol vsta vstp c d ? f/ ? v ? f/ ? ic ? f/ ? c g v hho r leak condition t sta 5sec (v ss ) t stp 10sec (v ss ) including the parasitic capacity inside the ic v ss =-1.8 to -3.5v c g =5 to 25pf c g =5pf (v ss ) between osc1 and v dd , and between v ss and osc1 S1C60L05 ? 1: items enclosed in parentheses ( ) are those used when operating at heavy load protection mode. unit v v pf ppm ppm ppm v m ? (unless otherwise specified: v dd =0v, v ss =-1.5v, crystal: q13mc146, c g =25pf, c d =built-in, ta=25 c) max. 5 10 -2.0 typ. 20 min. -1.2 -1.2 -10 40 200 characteristic oscillation start voltage oscillation stop voltage built-in capacitance (drain) frequency/voltage deviation frequency/ic deviation frequency adjustment range harmonic oscillation start voltage allowable leak resistance symbol vsta vstp c d ? f/ ? v ? f/ ? ic ? f/ ? c g v hho r leak condition t sta 5sec (v ss ) t stp 10sec (v ss ) including the parasitic capacity inside the ic v ss =-1.2 to -2.0v (-0.9) * 1 c g =5 to 25pf c g =5pf (v ss ) between osc1 and v dd , and between v ss and osc1 s1c60n05 (cr) unit % v ms v (unless otherwise specified: v dd =0v, v ss =-3.0v, r cr =480k ? , ta=25 c) max. 20 typ. 65khz 3 min. -20 -1.8 -1.8 characteristic oscillation frequency dispersion oscillation start voltage oscillation start time oscillation stop voltage symbol f osc vsta t sta vstp condition v ss =-1.8 to -3.5v S1C60L05 (cr) unit % v ms v (unless otherwise specified: v dd =0v, v ss =-1.5v, r cr =480k ? , ta=25 c) max. 20 typ. 65khz 3 min. -20 -1.2 -1.2 characteristic oscillation frequency dispersion oscillation start voltage oscillation start time oscillation stop voltage symbol f osc vsta t sta vstp condition v ss =-1.2 to -2.0v
9 s1c60n05 pad layout diagram of pad layout pad coordinates y x (0, 0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 53 52 51 50 49 48 47 46 45 44 43 42 die no. 2.58 mm 2.95 mm pad no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 pad no. 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 pad name adout seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 test reset seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 com0 com1 com2 com3 pad name v l3 v l2 v l1 ca cb v ss v dd osc1 osc2 v s1 p00 p01 p02 p03 k00 k01 k02 k03 r00 r01 r02 r03 rs th1 th2 cs x 644 511 381 251 121 -9 -139 -269 -399 -529 -659 -789 -919 -1,306 -1,306 -1,306 -1,306 -1,306 -1,306 -1,306 -1,306 -1,306 -1,306 -1,306 -1,306 -1,306 -1,306 x -1,259 -1,129 -998 -868 -737 -81 50 185 337 490 863 993 1,123 1,253 1,306 1,306 1,306 1,306 1,306 1,306 1,306 1,306 1,306 1,306 1,306 1,306 y 1,121 1,121 1,121 1,121 1,121 1,121 1,121 1,121 1,121 1,121 1,121 1,121 1,121 987 854 724 597 464 334 204 74 -56 -186 -371 -509 -639 -769 y -1,121 -1,121 -1,121 -1,121 -1,121 -1,121 -1,121 -1,121 -1,121 -1,121 -1,121 -1,121 -1,121 -1,121 -665 -535 -404 -274 -49 81 310 440 582 721 857 1,038 (unit: m)
10 s1c60n05 basic external connection diagram piezo buzzer single terminal driving note: the above table is simply an example, and is not guaranteed to work. ca cb v l1 v l2 v l3 v dd osc1 osc2 v s1 reset test vss c 1 c g c 2 x'tal 1.5 v or 3.0 v piezo buzzer r01 k00 k03 p00 p03 r00 r02 r03 i i/o o seg0 seg19 com0 com3 lcd panel s1c60n05/60l05 [the potential of the substrate (back of the chip) is v dd .] coil cp rs th1 cs r s th1 th2 th2 c ad capacitors (c 3 and c 4 ) are connected. connection depending on power supply and lcd panel specification. x'tal c g c 1 , c 2 , c 3 , c 4 cp th1, th2 r s c ad crystal oscillator trimmer capacitor capacitor capacitor thermistor resistor capacitor 32,768 hz ci(max) = 35 k ? 5 25 pf 0.1 f 3.3 f 50 k ? 49.8 k ? 2,200 pf
11 s1c60n05 piezo buzzer direct driving r00 k00 k03 p00 p03 r02 r03 i i/o o seg0 seg19 com0 com3 lcd panel r01 ca cb v l1 v l2 v l3 v dd osc1 osc2 v s1 reset test vss 1.5 v or 3.0 v s1c60n05/60l05 [the potential of the substrate (back of the chip) is v dd .] rs th1 cs r s th1 th2 th2 c ad r 1 r 2 piezo buzzer c 1 c g c 2 x'tal cp capacitors (c 3 and c 4 ) are connected. connection depending on power supply and lcd panel specification. x'tal c g c 1 , c 2 , c 3 , c 4 cp th1, th2 r s r 1 , r 2 c ad crystal oscillator trimmer capacitor capacitor capacitor thermistor resistor resistor capacitor 32,768 hz ci(max) = 35 k ? 5 25 pf 0.1 f 3.3 f 50 k ? 49.8 k ? 100 ? 2,200 pf note: the above table is simply an example, and is not guaranteed to work.
s1c60n05 notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 2001 all right reserved. seiko epson corporation electronic devices marketing division ic marketing & engineering group ed international marketing department europe & u.s.a. 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5812 fax : 042-587-5564 ed international marketing department asia 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5814 fax : 042-587-5110 http://www.epson.co.jp/device/ epson electronic devices website first issue february, 1998 m printed july, 2001 in japan l package plastic qfp6-60pin 14 0.2 17.6 0.4 31 45 14 0.2 17.6 0.4 16 30 index 0.35 0.1 15 1 60 46 2.7 0.1 0.1 3.1 max 1.8 0.85 0.2 0 10 0.15 0.05 0.8 (unit: mm)

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